Low temperature co-fired ceramic with improved shrinkage control

ABSTRACT

A low temperature co-fired ceramic assembly (LTCC) with a constraining core of differing dielectric constants that minimizes shrinkage of the outer ceramic layers during firing. The ceramic assembly has a planar ceramic core. The core has a first ceramic layer with a first dielectric constant and a second ceramic layer adjacent to the first ceramic layer. The second ceramic layer has a second dielectric constant. A third ceramic layer has a third dielectric constant. A fourth ceramic layer has a fourth dielectric constant. The ceramic core is located between the third and the fourth ceramic layers. Several electrically conductive vias extend through the first, second, third and fourth ceramic layers. Several circuit features are located on the first, second, third and fourth ceramic layers. The vias electrically connect the circuit features on the layers.

CROSS-REFERENCE TO RELATED AND CO-PENDING APPLICATIONS AND PATENTS

[0001] This application is related to U.S. Pat. No. 6,205,032.

BACKGROUND

[0002] 1. Field of the Invention

[0003] This invention generally relates to ceramic electronic packaging.Specifically, there is a multilayered low temperature co-fired ceramicassembly (LTCC) with a constraining core to minimize shrinkage of outerceramic layers during firing. The ceramic layers have differentdielectric constants to allow fabrication of high density capacitors andother electronic components.

[0004] 2 Description of Related Art

[0005] Various devices are well known for providing ceramic packages forsemiconductor devices and passive components. One of the prior artdesigns is a low temperature co-fired ceramic (LTCC) substrate. The LTCCceramic is made of layers of ceramic material, which in an unfiredstate, are called green tapes. Circuit lines, resistors, capacitors,bonding pads and vias are created on the surface and in holes of thegreen tapes by conventional thick film screening techniques. The layersare stacked on top of each other laminated and fired at a relatively lowtemperature in a furnace. During firing, the LTCC shrinks along the x, yand z axes typically 10-25 percent depending upon the LTCC formulation.

[0006] Despite the advantages of the prior art LTCC designs, problemsoccur with the registration or alignment of the circuit lines andcomponents on the exterior surfaces during manufacturing. During firing,the shrinkage of the LTCC causes the external features to vary withrespect to true position. This true position error can causemisalignment when attaching components or printing post-fire materials,resulting in a defective part that is non-repairable and has to bediscarded.

[0007] Another problem with LTCC electronic packages occurs in thefabrication of buried capacitors within the package. It is desirable tohave a high dielectric constant between capacitor electrodes so that agiven capacitance can be achieved without large electrodes. At the sametime, it is desirable for the circuit lines that attach to the capacitorelectrodes to be located on a low dielectric constant substrate toreduce unwanted parasitic effects such as coupling to other lines orembedded components.

[0008] Several attempts have been made in the prior art to solve some ofthese problems. U.S. Pat. No. 5,518,969, shows a process for producinglow shrink ceramic compositions. U.S. Pat. No. 5,144,526, shows a lowtemperature co-fired ceramic structure containing buried capacitors.U.S. Pat. No. 5,745,334, shows a capacitor formed within a printedcircuit board. None of these patents have been able to overcome all ofthe problems of the prior art.

SUMMARY

[0009] It is a feature of the invention to provide a low temperatureco-fired ceramic assembly (LTCC) with a constraining core of differingdielectric constants to minimize shrinkage of outer ceramic layersduring firing.

[0010] A further feature of the invention is to provide a multilayeredlow temperature co-fired ceramic assembly including a planar ceramiccore. The core has a first ceramic layer with a first dielectricconstant and a second ceramic layer adjacent to the first ceramic layer.The second ceramic layer has a second dielectric constant. A thirdceramic layer has a third dielectric constant. A fourth ceramic layerhas a fourth dielectric constant. The ceramic core is located betweenthe third and the fourth ceramic layers. Several electrically conductivevias extend through the first, second, third and fourth ceramic layers.Several circuit features are located on the first, second, third andfourth ceramic layers. The vias electrically connect the circuitfeatures on the layers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a side cross sectional view of the preferred embodimentof a low temperature co-fired ceramic assembly (LTCC) with improvedregistration.

[0012]FIG. 2 is a diagram showing an assembly sequence of the assemblyof FIG. 1.

[0013]FIG. 3 is a diagram showing an alternative assembly sequence.

[0014] It is noted that the drawings of the invention are not to scale.

DETAILED DESCRIPTION

[0015] Referring to FIGS. 1 and 2, a multilayered low temperatureco-fired ceramic (LTCC) assembly 10 is shown. LTCC ceramic layers 14 and16 have outer surfaces 14A, 14B and 16A and 16B, respectively. Layers 14and 16 are conventional LTCC green tapes. An example of layers 14 and 16is 951 Green Tape (tm) commercially available from Dupont Corporation,Electronic Materials Division, Wilmington, Del. Layers 12 and 16, bythemselves, shrink from 8 to 12 percent during firing in all axes (bothin plane and perpendicular to the layer). Layers 14 and 16 can havedifferent dielectric constants or the same dielectric constants. Forexample, layers 14 and 16 can have dielectric constants that typicallyrange from 4 to 2000.

[0016] Various circuit features can be included on layers 14 and 16 ifdesired. The circuit features patterned on layers 14 and 16 are callednon-critically shrinking circuit features. They are larger in dimension,spaced farther apart and have lesser registration requirements than thecircuit features on the other layers. A buried resistor 27 is shown onsurface 16A. A via 28 connects resistor 27 with bottom surface 18B. Aburied inductor 34 is shown on surface 16B. Another via 28 connectsinductor 34 to bottom surface 18B. Capacitor electrodes 25 are shown onlayers 14 and 16. These are some examples of the circuit features andcomponents that can be fabricated on assembly 10. Resistors 27, inductor34 and vias 28 are made from conventional thick film conductor materialsand are applied by conventional thick film screening and curingtechniques. After circuit features have been applied, layers 14 and 16would be stacked on top of each other or laminated and fired in afurnace to form a ceramic core 15.

[0017] LTCC ceramic layers 12 and 18 have outer surfaces 12A, 12B and18A and 18B, respectively. Layers 12 and 18 are conventional LTCC greentapes. An example of layers 12 and 18 is 951 Green Tape (tm)commercially available from Dupont Corporation, Electronic MaterialsDivision, Wilmington, Del. Layers 12 and 18 can have differentdielectric constants or the same dielectric constants. For example,layers 12 and 18 can have dielectric constants that typically range from5 to 60.

[0018] Capacitor electrodes 25 are located on surface 12A, 12B, 14B and16B. Electrodes 25 form a capacitor. A via 28 connects buried electrode25 to bond pad 32 on outer surface 18B. A circuit line 26 is located onsurface 12A. Via 28 connects an end of circuit line 26 to bond pad 32 onouter surface 18B. Bond pads 32 can connect to a semiconductor device ifdesired. A resistor 27 is shown on surface 18B. Circuit lines 26, bondpads 32 and vias 28 connect with other circuit lines (not shown) orcomponents (not shown) on the LTCC device 10. The circuit features onlayers 12 and 18 are made from conventional thick film conductormaterials and are applied by conventional thick film screening andcuring techniques. These circuit features and components on layers 12and 18 are patterned in a high density configuration with smalldimensions and have to be held to precise tolerances for post-fireprocessing. If shrinkage is not precisely controlled, post-firematerials or placed components will be mis-registered, resulting in anelectrical open or short.

[0019] After circuit features have been applied to layers 12 and 18,ceramic core 15 is stacked on layer 18 and layer 12 is stacked orlaminated on top of ceramic core 15 to form assembly 10. The assembly 10is typically laminated in a press. Assembly 10 is then fired in afurnace to form assembly 10. Again, these circuit features andcomponents have to be held to precise registration and tolerance. In thecase of a mis-alignment among the circuit components, an open or a shortmay result. The combination of the fired ceramic core 15 between thelayers 12 and 18 causes a change in the shrinkage rate of the layers 12and 18 during firing. Layers 12 and 18 shrink less than 1.0 percent inthe x and y axes (parallel to the planar layer) during firing. Layers 12and 18 do not shrink at their normal 10 to 25 percent rate in the z-axisdirection. Layers 12 and 18 shrink at a much higher rate in the z-axis(perpendicular to the planar layers) of about 40 to 60 percent in orderto arrive at a normal density after firing. Layers 12 and 18 shrink asto conserve mass. The ceramic core 15 maintains its fired dimensions orshrinks slightly on the order of less than 1.0 percent in the x, y and zaxes. Ceramic core 15 constrains the shrinkage of layers 12 and 18 tothat of the ceramic core 15 in the x and y directions. The resultingassembly 10 after firing is able to have higher densities, smallerdimensions and better hold registration and tolerances for circuitfeatures placed on layers 12, 14, 16 and 18. The better registrationresults in improved yields, better quality, less rejects, less scrap andlower costs of manufacturing.

[0020] Using a mix of layers with different dielectric constants allowsa greater range of electronic component values to be fabricated onassembly 10. For example, if layers 14 and 16 have a dielectric constantof 50.0, capacitor electrodes that are 100 by 100 mils, layer 12 is 1.7mils thick and there are 3 plates as shown in FIG. 1. Then a capacitanceof 132 picofarads is obtained. Using higher dielectric constants allowscapacitors of larger capacitance values to be buried within assembly 10.

[0021] At the same time, using a lower dielectric constant material witha dielectric constant such as 7.0 on layers 12 and 18 provides for lesscross talk noise and electromagnetic coupling from devices and circuitlines on layers 12 and 18 to adjacent and buried circuit lines anddevices. Using a different dielectric constant on different layers alsoallows the impedance of circuit lines 26 to be adjusted for a given linewidth. LTCC assembly 10, of FIGS. 1 and 2 can be assembled as follows:The first step is to punch vias 28 into layers 12, 14, 16 and 18. Thevias 28 are then screen filled with a conductive material on each oflayers 12, 14, 16 and 18. Next, electrodes 25, resistors 27, circuitlines 26, bond pads 32 and inductors 34 would be screened onto surfaces12A, 12B, 14A, 14B, 16A, 16B, 18A and 18B. Layers 14 and 16 would bestacked and laminated under heat and pressure onto each other. Layers 14and 16 are fired in a furnace at a temperature between 700 and 1000degrees Celsius to form ceramic core 15.

[0022] Ceramic core 15 is stacked onto layer 18 and layer 12 is stackedonto ceramic core 15. Next, Layers 12, 18 and core 15 are laminatedunder heat and pressure. Layers 12, 18 and ceramic core 15 are fired ina furnace at a temperature between 700 and 1000 degrees Celsius tocomplete assembly 10.

[0023] Turning now to FIG. 3, an alternative assembly sequence of amultilayered low temperature co-fired ceramic (LTCC) assembly 62 isshown. Assembly 62 is similar to assembly 10 except that it has moreceramic layers with differing dielectric constants.

[0024] Layers 42, 44, 46, 48, 50, 52, 54 and 56 are conventional LTCCgreen tapes. Layers 42, 44, 46, 48, 50, 52, 54 (42-54) can havedifferent dielectric constants or some of the layers may have the samedielectric constants. The layers 42-54 can have dielectric constantsthat typically range from 4 to 2000. For example, the layers could havethe following dielectric constants: Layer Dielectric Constant 42 35 4450 46 50 48 35 50  7 52 20 54 20 56  7

[0025] Layers 42-54 would have circuit features and vias applied thesame as for assembly 10. Layers 42, 44, 46 and 48 are stacked, laminatedand fired to form a ceramic core 60. Next, layers 54 and 56 are stackedand core 60 placed on top. Next, layers 52 and 50 are stacked onto core60 to form ceramic assembly 62. Assembly 62 is laminated in a press andfired in a furnace. The ceramic layers in assembly 62 having differingdielectric constants allows the fabrication of a wider range ofcapacitance and component values.

[0026] One of ordinary skill in the arts electronic packaging andelectronic ceramics, will realize many advantages from using thepreferred embodiment. Further, one of ordinary skill in the art willrealize that there are many different ways of accomplishing thepreferred embodiment. For example, it is contemplated that more than twolayers 14 and 16 could be stacked to form core 15. Similarly, more thantwo layers 12 and 18 could be stacked on core 15. It also is possible tostack several units of assembly 10 on each other and then fire theoverall unit.

[0027] Even though the embodiment discusses the use of certain circuitfeatures, other circuit features or passive elements could be used suchas waveguides, resonators, or mixers. Other circuit features could beincluded like coupled structures such as baluns mutual inductors ordirectional couplers. Further, it is contemplated that semiconductordevices could be mounted on the outer surfaces 12A or 18A.

[0028] While the invention has been taught with specific reference tothese embodiments, someone skilled in the art will recognize thatchanges can be made in form and detail without departing from the spiritand the scope of the invention. The described embodiments are to beconsidered in all respects only as illustrative and not restrictive. Thescope of the invention is, therefore, indicated by the appended claimsrather than by the foregoing description. All changes that come withinthe meaning and range of equivalency of the claims are to be embracedwithin their scope.

What is claimed is:
 1. A multilayered low temperature co-fired ceramicassembly comprising: a) a planar ceramic core including: a1) a firstceramic layer having a first dielectric constant; a2) a second ceramiclayer adjacent to the first ceramic layer, the second ceramic layerhaving a second dielectric constant; b) a third ceramic layer having athird dielectric constant; c) a fourth ceramic layer having a fourthdielectric constant, the ceramic core located between the third and thefourth ceramic layers; d) a plurality of electrically conductive viasextending through the first, second, third and fourth ceramic layers;and e) a plurality of circuit features located on the first, second,third and fourth ceramic layers, the vias electrically connecting thecircuit features on the layers.
 2. The multilayered low temperatureco-fired ceramic assembly according to claim 1, wherein the circuitfeatures are selected from the group consisting of: a) resistors; b)capacitors; c) circuit lines; d) inductors; e) bond pads; or f) coupledstructures.
 3. The multilayered low temperature co-fired ceramicassembly according to claim 1, wherein the first dielectric constant hasa value between 4 and
 2000. 4. The multilayered low temperature co-firedceramic assembly according to claim 1, wherein the second dielectricconstant has a value between 4 and
 2000. 5. The multilayered lowtemperature co-fired ceramic assembly according to claim 1, wherein thethird dielectric constant has a value between 4 and
 2000. 6. Themultilayered low temperature co-fired ceramic assembly according toclaim 1, wherein the fourth dielectric constant has a value between 4and
 2000. 7. The multilayered low temperature co-fired ceramic assemblyaccording to claim 1, wherein the ceramic core shrinks in three axesduring firing.
 8. The multilayered low temperature co-fired ceramicassembly according to claim 7, wherein the third and fourth ceramiclayers shrink so as to converse mass in a direction perpendicular to theplanar layers.
 9. The multilayered low temperature co-fired ceramicassembly according to claim 1, wherein the first and second dielectricconstants are the same.
 10. The multilayered low temperature co-firedceramic assembly according to claim 1, wherein the third and fourthdielectric constants are the same.
 11. The multilayered low temperatureco-fired ceramic assembly according to claim 1, wherein the first andfourth dielectric constants are the same.
 12. The multilayered lowtemperature co-fired ceramic assembly according to claim 1, wherein thesecond and third dielectric constants are the same.
 13. The multilayeredlow temperature co-fired ceramic assembly according to claim 8, whereinthe third and fourth ceramic layers shrink less than 1.0% in a directionparallel to the planar layers.
 14. A multi-layered ceramic assemblycomprising: a) a planar ceramic core that undergoes a first oven firingprior to assembly, the ceramic core sintering in all axes during thefirst oven firing, the ceramic core including: a1) a first ceramic layerhaving top and bottom surfaces, the first ceramic layer having a firstdielectric constant; a2) a second ceramic layer attached to the firstceramic layer, the second ceramic layer having top and bottom surfacesand a second dielectric constant; b) a third ceramic layer attached tothe first ceramic layer, the third ceramic layer having top and bottomsurfaces and a third dielectric constant; c) a fourth ceramic layerattached to the second ceramic layer, the fourth ceramic layer having atop and bottom surface and a fourth dielectric constant, the ceramiccore located between the bottom surface of the third ceramic layer andthe top surface of the fourth ceramic layer, the third and fourthceramic layers constrained from sintering in all axes by the ceramiccore during a second oven firing; d) a plurality of electricallyconductive vias extending through the first, second, third and fourthceramic layers; and e) a plurality of circuit features located on thefirst, second, third and fourth ceramic layers, the vias electricallyconnecting the circuit features on the layers.
 15. The multilayeredceramic assembly according to claim 14, wherein the circuit features areselected from the group consisting of: a) resistors; b) capacitors; g)circuit lines; d) inductors; e) bond pads; or f) coupled structures. 16.The multilayered ceramic assembly according to claim 15, wherein thelayers are laminated prior to firing
 17. A method of making amultilayered ceramic assembly, comprising: a) providing a first andsecond planar ceramic layer having a first and second dielectricconstant, respectively; b) punching a plurality of via holes in thefirst and second ceramic layers; c) filling the via holes with aconductive composition; d) screen printing a plurality circuit featureson the first and second layers; e) stacking the first ceramic layer ontothe second ceramic layer; f) firing the first and second ceramic layersin an oven to form a ceramic core; g) providing a third and fourthplanar ceramic layer having a third and fourth dielectric constant,respectively; h) punching a plurality of via holes in the third andfourth ceramic layers; i) filling the via holes with a conductivecomposition; j) screen printing a plurality of high density circuitfeatures on the third and fourth ceramic layers; k) stacking the ceramiccore onto the fourth ceramic layer and stacking the third ceramic layeronto the ceramic core; and l) firing the third and fourth ceramic layersand the ceramic core in a furnace such that the ceramic assembly isformed.
 18. The method according to claim 17, wherein the ceramic coreis fired at a temperature between 700 and 1000 degrees Celsius.
 19. Themethod according to claim 17, wherein the ceramic assembly is fired at atemperature between 700 and 1000 degrees Celsius.
 20. The methodaccording to claim 17, wherein the ceramic assembly is pressed afterstacking.